1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, it relates to a method of manufacturing a semiconductor device the respective elements of which are isolated by grooves having flat tops of small steps.
2. Description of the Prior Art
A semiconductor integrated circuit includes large numbers of active elements and passive elements such as transistors, diodes and resistors. Since these elements are formed within an identical semiconductor substrate, they need to be electrically isolated from one another.
In order to achieve the electrical isolation of the respective elements formed in the substrate, several methods have been proposed. Among them, a method called the "pn-junction isolation" has heretofore been employed most extensively.
This method exploits the fact that a pn-junction exhibits a high resistance when reverse-biased. It consists in forming pn-junctions between the elements so as to isolate the respectively adjacent elements.
As stated above, the pn-junction isolation has heretofore been the most common as the expedient for isolating the elements in semiconductor devices. Since, however, it involves such problems as a large required area and large parasitic capacitances, it is difficult of application to a semiconductor device having a high packaging density.
In order to solve such problems, a method called the "groove isolation" has been proposed.
This method consists in forming grooves, for example, U-shaped or V-shaped in section within the semiconductor substrate so as to isolate the respective elements by means of the grooves. It includes two cases; one case where the groove is entirely filled up with an insulator, and the other case where an insulating layer is formed on the side surface and bottom surface of the groove and where the remaining part is filled with polycrystalline silicon or the like. (Hereunder, the isolation employing the U-shaped or V-shaped grooves shall be written the "U-groove or V-groove isolation" in this specification.)
As compared with the aforementioned pn-junction isolation, this groove isolation has various merits such as a small required area, small parasitic capacitances and a great isolation voltage. However, it involves the following problems, the solutions of which are eagerly desired.
In case of performing the U-groove isolation, it is common practice to adopt a method in which, as illustrated in FIG. 1, a groove or recess is formed in a semiconductor substrate 1 in advance, a deposit material 2 such as insulator and polycrystalline silicon is deposited on the whole surface of the substrate by a well-known process such as the CVD (chemical vapor deposition), a mask 3 covering the groove is formed and the film of the deposit material 2 is chemically etched. (In case of employing polycrystalline silicon as the filling material 2, as will be described later, the bottom surface and side surface of the groove are covered with a thin insulating film, whereupon the polycrystalline silicon is deposited to fill up the groove. In order to facilitate understanding, however, the formation of the thin insulating film is not explained here.)
When the filling material film 2 is etched in the above method, a bulge 4 of the filling material appears at an end part of the groove and hampers the flattening of the upper surface of the groove as illustrated in FIG. 2. Especially, when the mask 3 for the selective etching deviates from the pattern of the substrate, there is the disadvantage that the bulge 4 becomes still larger.
When a wiring running on such bulge is formed, it is liable to disconnection due to the bulge. It is therefore difficult to form a semiconductor integrated circuit having a high reliability.
Accordingly, a method which can fill up the groove or recess provided in the semiconductor substrate into a flat upper surface is earnestly requested.